library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Register_8bit is
    Port ( 
        Clock : in STD_LOGIC;
        Reset : in STD_LOGIC;
        Data_in : in STD_LOGIC_VECTOR (7 downto 0);
        Data_out : out STD_LOGIC_VECTOR (7 downto 0)
    );
end Register_8bit;
 
architecture Behavioral of Register_8bit is
begin
    process(Clock, Reset)
    begin
        if Reset = '1' then
            Data_out <= "00000000";
        elsif rising_edge(Clock) then
            Data_out <= Data_in;
        end if;
    end process;
end Behavioral;

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